Low-Energy Encoding for Deep-Submicron Address Buses

In this paper, we introduce a new encoding scheme that explicitly targets the minimization of the bus energy due to the crosstalk capacitances between adjacent bus lines. The key transformation operated by the code consists of a permutation of the bus lines, implemented directly during physical design; as a desirable consequence, no additional encoding/decoding logic is required at the bus boundaries, thus implying that no latency penalty is introduced on the processor-memory path. An additional feature of the permutation-based code is that the encoding function can be determined without any knowledge of the binary stream being transmitted. Therefore, the code can be e ectively exploited in general-purpose computing systems. The proposed code works best on address buses; savings obtained for di erent address traces generated by two di erent processors are in the order of 26% with respect to the unencoded streams.